Embedded Base Boot Requirements (EBBR) Specification

Copyright © 2017-2021 Arm Limited and Contributors.

Copyright © 2021 Western Digital Corporation or its affiliates, 2021

This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.

Table 1 Revision History

Date	Issue	Changes
20 Sep 2017	0.51	Confidentiality Change, EBBR version 0.51
12 Jul 2018	0.6	Relicense to CC-BY-SA 4.0 Added Devicetree requirements Added Multiprocessor boot requirements Transitioned to reStructuredText and GitHub Added firmware on shared media requirements RTC is optional Add constraints on sharing devices between firmware and OS Add large note on implementation of runtime modification of non-volatile variables
18 Oct 2018	0.7	Add AArch32 details Refactor Runtime Services text after face to fact meeting at Linaro Connect YVR18
12 Mar 2019	0.8	Update language around SetVariable() and what is available during runtime services Editorial changes preparing for v1.0
31 Mar 2019	1.0	Remove unnecessary UEFI requirements appendix Allow for ACPI vendor id in firmware path
5 Aug 2020	1.0.1	Update to UEFI 2.8 Errata A Specify UUID for passing DTB Typo and editorial fixes Document the release process
23 Apr 2021	2.0.0	Reduce the number of UEFI required elements needed for compliance. Add requirement for UpdateCapsule() runtime service. Updated firmware shared storage requirements Refined RTC requirements Fixed ResetSystem() to correctly describe failure condition
6 Aug 2021	2.0.1	Update UEFI version to 2.9 Update Devicetree spec version to v0.3 Add RISC-V platform text Temporarily drop ESRT requirement Fix typos

• 1. About This Document
  • 1.1. Introduction
  • 1.2. Guiding Principles
  • 1.3. Scope
  • 1.4. Conventions Used in this Document
  • 1.5. Cross References
  • 1.6. Terms and abbreviations
    • 1.6.1. AARCH32
    • 1.6.2. AARCH64
    • 1.6.3. RISC-V
• 2. UEFI
  • 2.1. UEFI Version
  • 2.2. UEFI Compliance
    • 2.2.1. Required Elements
    • 2.2.2. Required Platform Specific Elements
    • 2.2.3. Required Global Variables
    • 2.2.4. Block device partitioning
  • 2.3. UEFI System Environment and Configuration
    • 2.3.1. AArch64 Exception Levels
      • 2.3.1.1. UEFI Boot at EL2
      • 2.3.1.2. UEFI Boot at EL1
    • 2.3.2. RISC-V Privilege Levels
      • 2.3.2.1. UEFI Boot at S mode
      • 2.3.2.2. UEFI Boot at HS mode
      • 2.3.2.3. UEFI Boot at VS mode
  • 2.4. UEFI Boot Services
    • 2.4.1. Memory Map
    • 2.4.2. Configuration Tables
      • 2.4.2.1. EFI Conformance Profile Table
      • 2.4.2.2. Devicetree
    • 2.4.3. UEFI Secure Boot (Optional)
  • 2.5. UEFI Runtime Services
    • 2.5.1. Runtime Device Mappings
      • 2.5.1.1. Real-time Clock (RTC)
    • 2.5.2. UEFI Reset and Shutdown
    • 2.5.3. Runtime Variable Access
    • 2.5.4. Firmware Update
• 3. Privileged or Secure Firmware
  • 3.1. AArch32 Multiprocessor Startup Protocol
  • 3.2. AArch64 Multiprocessor Startup Protocol
  • 3.3. RISC-V Multiprocessor Startup Protocol
• 4. Firmware Storage
  • 4.1. Partitioning of Shared Storage
    • 4.1.1. GPT partitioning
      • 4.1.1.1. MBR partitioning
  • 4.2. Firmware Partition Filesystem
    • 4.2.1. Fixed Shared Storage
    • 4.2.2. Removable Shared Storage
• 5. Bibliography